The present invention disclosed herein relates to a digital-to-analog converter (DAC), and more particularly, to a DAC with a reduced circuit area.
A digital value is expressed numerically using binary logic, where each bit has one of two possible logic values, i.e., 0 and 1. A digital value can be one of several predetermined values within a range. On the contrary, an analog value may be any value within a continuous range. Physical variations such as temperature, pressure, intensity of light, voice signal, position, circulation speed, flow rate, etc. are perceived by humans and conventional sensors as analog values.
All analog signals inputted to a digital system should be converted into digital format in advance. Likewise, an output of the digital system is in digital format, but such output can be converted into analog format as needed.
Generally, digital-to-analog (D/A) conversion is a procedure of receiving a digital value represented by a digital code and then converting it into a predetermined voltage or current in proportion to the digital value. During D/A conversion, a reference voltage Vref is used in determining maximum output or maximum value that a D/A converter (DAC) produces. 16 binary numbers can be expressed using 4-bits to represent output voltages of the DAC. An actual analog output voltage Vout is proportional to an input binary number, and is expressed as a multiple of the binary number. Strictly, when the reference voltage Vref is a constant, the output voltage Vout has only a discrete value, e.g., one of 16 possible voltage levels, so that the output of the DAC is not an analog value. However, the number of possible output values can be increased by increasing the number of bits of input data. A larger number of possible output values in the output range reduces the difference between DAC output values.
When the DAC input includes a relatively large number of bits, the DAC provides a relatively high-resolution output. A circuit area of the DAC is increased proportionally with resolution. That is, as the number of bits of the digital signal increases by 1 bit, an area of a decoder in the DAC increases by twice. Thus, since a chip size of the DAC increases.
For example, provided that the input data is 8 bit in a conventional R-type (resistive string) DAC, the DAC is configured with 28 resistors, 28 metals and one 256×1 decoder. Herein, the metals denote signal lines that transmit input signals decoded by the decoder when the DAC is realized in a wafer or a chip. In case of fabricating a 10-bit DAC, 1,024 resistors, 1,024 metals and one 1024×1 decoder are needed. Therefore, in comparison of a decoder of the 10-bit DAC with that of the 8-bit DAC, the decoder of 10-bit DAC is four times greater in size than the decoder of 8-bit DAC, and the decoder of 10-bit DAC has four times the number of resistors and metals of the 8-bit DAC.
Other problems also exist with conventional DAC's. For example, conventional DAC's typically implement a sample and hold circuit using an operational amplifier (OP-AMP). Unfortunately, parasitic capacitance at an input terminal of the OP-AMP has an undesirable effect on an output of the DAC when modulating a voltage level of a non-inverting input terminal of the OP-AMP.